1. Field of the Invention
The present invention relates to a power semiconductor device, and more particularly to a semiconductor device having a high withstand voltage.
2. Description of the Revelant Art
Heretofore, high-speed, high-withstand voltage semiconductor devices are used in apparatus for switching large currents in power supplies or the like. FIG. 33 of the accompanying drawings shows a semiconductor chip 101 of MOSFET which is generally used as one of those conventional semiconductor devices.
As shown in FIG. 33, the semiconductor chip 101 is made of a single crystal of silicon and has a drain layer 102 comprising an nxe2x88x92 layer 1021 of high resistance, an nxe2x88x92 layer 1022 of low resistance which is of the same conductivity type as the nxe2x88x92 layer 1021, and a highly conductive region 103.
The nxe2x88x92 layer 1022 is positioned centrally in the drain layer 102, the n+ layer 1022 in a back side of the drain layer 102, and the highly conductive region 103 in a face side of the drain layer 102. If an n type is a first conductivity type, then a number of p-type diffused base layers 108 which are of a second conductivity type are disposed on the surface of the highly conductive region 103.
The diffused base layers 108, each of a square shape, are arranged in a matrix. As shown in FIG. 34 of the accompanying drawings, each of the diffused base layers 108 comprises a central main diffused layer 106 having a large diffusion depth and a channel region 107 having a small diffusion depth and surrounding the main diffused layer 106. Therefore, each of the diffused base layers 108 is deeper in its central area and shallower in its peripheral area.
A ring-shaped n-type diffused source layer 105 is disposed in each of the diffused base layers 108. A gate insulating film 104 comprising a silicon oxide film and a gate electrode film 110 are deposited in the order named on the surfaces of the channel regions 107. When a positive voltage is applied to the gate electrode film 110, an n-type inverted layer is developed in the surface of the p-type channel region 107, electrically connecting the diffused source layer 105 and the highly conductive region 103 to each other.
The semiconductor chip 101 also has a source electrode film 111 and a drain electrode film 112 which are prevented from being short-circuited by an interlayer insulating film 115.
The MOSFET shown in FIG. 33 has a higher operating speed than bipolar transistors, and suffers a small current concentration upon transition from a conducted state to a cut-off state, allowing a semiconductor device having a high withstand voltage to be easily fabricated.
When a conducting current flows in the semiconductor chip 101, the resistance of the drain layer 102 and the resistance of a JFET between the diffused base layers 108 are effective enough to cause a larger loss than bipolar transistors.
With the highly conductive region 103 in the face side of the drain layer 102, the resistance of the drain layer 102 is reduced, resulting in a reduction in the forward resistance of the MOSFET. The withstand voltage of the MOSFET is lowered because a depletion layer is less liable to spread in the highly conductive region 103.
In a pn junction made up of the diffused base layer 108 and the highly conductive region 103, as shown in FIG. 35a of the accompanying drawings, depletion layers 120 tending to spread into the highly conductive region 103 are less liable to spread in the highly conductive region 103 as the highly conductive region 103 is of a higher concentration.
Generally, pn junctions are classified into planar junctions, cylindrical junctions, and spherical junctions in terms of the configuration of a diffused layer of higher concentration. Cylindrical junctions are formed on confronting sides of the channel regions 107, whereas spherical junctions are formed on vertexes of the channel regions 107.
It is known that the pn junctions have a withstand voltage which is progressively smaller in the order of planar junctions, cylindrical junctions, and spherical junctions. The withstand voltage of the pn junction between the diffused base layers 108 and the highly conductive region 103 is determined by the spherical junctions on vertexes of the diffused base layers 108. Particularly, an avalanche breakdown tends to occur on the surface of the highly conductive region 103.
If confronting diffused base layers 108 are displaced closely to each other until two depletion layers 120 extending in the highly conductive region 103 are brought into contact each other, then when a reverse bias greater than the voltage at which the depletion layers 120 contact each other is applied, the depletion layers 120 spread in their depth, and hence the withstand voltage is determined at a position deeper than the surface of the highly conductive region 103.
In this case, the withstand voltage is higher than if an avalanche breakdown occurs when the confronting diffused base layers 108 are spaced from other and before the depletion layers 120 contact each other.
With the conventional MOSFET, however, as shown in FIG. 35b of the accompanying drawings, a reverse biased state between the drain layer 102 and the diffused base layers 108 is so large that even when the depletion layers 120 are held in contact with each other between the sides of the channel regions 107, the depletion layers 120 are kept out of contact with each other between the vertexes of the channel regions 107 because the distance between the vertexes is large, so that the withstand voltage of the spherical junctions will not increase. The pn junctions are thus subjected to a breakdown in surface areas 111, tending to break the semiconductor device.
It is therefore an object of the present invention to provide a semiconductor device having a high withstand voltage.
Another object of the present invention is to provide a semiconductor device whose withstand voltage can be increased while preventing a conducting resistance from being increased.
According to the present invention, there is provided a semiconductor device having a drain layer of a first conductivity type formed in a semiconductor subtrate, the first conductivity type being either a p type or an n type of semiconductor, and a second conductivity type being the other of the p type or the n type, a diffused base layer of the second conductivity type formed in a surface of said drain layer, and a diffused source layer of the first conductivity type formed in a surface of said diffused base layer, said diffused base layer having a portion as a channel region between said diffused source layer and said drain layer, said channel region having on a surface thereof a gate insulating film and a gate electrode film, the arrangement being such that when a voltage is applied to said gate electrode film, forming an inverted layer in the surface of said channel region, said diffused source layer and said drain layer are electrically connected to each other by said inverted layer, characterized in that a portion of said drain layer which is connected to the diffused source layer by at least said inverted layer has a highly conductive region having a resistance lower than said drain layer and the same conductivity type as said drain layer, said highly conductive region having a surface surrounded by a diffused layer of the second conductivity type including said diffused base layer.
The surface of said highly conductive region may be divided into a plurality of regions by the diffused layer of the second conductivity type including said diffused base layer.
The diffused base layer may have a main diffused layer which is of the same conductivity type as said diffused base layer and is diffused to a depth greater than said diffused base layer, said highly conductive region being diffused to a depth greater than the depth to which said main diffused layer is diffused.
The semiconductor device may further comprise a diffused guard ring layer disposed around an outer peripheral portion of said diffused base layer, said diffused guard ring layer being of the same conductivity type as said diffused base layer and diffused to a depth greater than the depth to which said main diffused layer is diffused. The diffused guard ring layer may be held in contact with a base region. Another diffused guard ring layer may be disposed outside of the above diffused guard ring layer in spaced relationship thereto.
The surface of the highly conductive region of the first conductivity type may have an outer peripheral portion held in contact with said diffused layer of the second conductivity type which includes the diffused guard ring layer and the diffused base layer. The highly conductive region may be brought into contact with the diffused layer of the second conductivity type when a window is opened in an insulating film for forming an impurity layer to form the highly conductive region, or the highly conductive region and the diffused layer of the second conductivity type may be brought into contact with each other by the diffusion of an impurity in the lateral direction of the substrate when an impurity layer is diffused to form the highly conductive region.
Furthermore, a drain electrode film may be disposed on either a face side or a back side of said semiconductor substrate and electrically connected to said drain layer.
With the above arrangement of the present invention, if a first conductivity type is either a p type or an n type of semiconductor, and a second conductivity type being the other of the p type or the n type, then a diffused base layer of the second conductivity type is formed in a surface of a drain layer of the first conductivity type, and a diffused source layer of the first conductivity type is formed in said diffused base layer of the second conductivity type, among said diffused layer of the second conductivity type, regions between said diffused source layer and said drain layer being a channel region.
The channel region has on a surface thereof a gate insulating film and a gate electrode film. When a voltage is applied to said gate electrode film, forming an inverted layer in the surface of said channel region, said diffused source layer and said drain layer are electrically connected to each other by said inverted layer, and a current flows between the diffused source layer and the drain layer.
A surface portion of said drain layer which is connected to the diffused source layer by said inverted layer has a highly conductive region having a resistance lower than that in deep portion of said drain layer, reducing a conducting resistance.
In conventional semiconductor devices, the diffused base layer of the second conductivity type is surrounded by the highly conductive region. According to the present invention, however, the highly conductive region is surrounded by the diffused base layer of the second conductivity type. Therefore, a pn junction between the highly conductive region and the diffused base layer of the second conductivity type has no spherical junction, and has a high withstand voltage. In the pn junction, the depletion layer in the highly conductive region spreads into the highly conductive region from the outer peripheral portion thereof.
Since no spherical junction is present, the impurity concentration of the highly conductive region can be increased while maintaining its high withstand voltage. The withstand voltage is not reduced even if the highly conductive region is deeply formed. Particularly if the diffused base layer of the second conductivity type is joined to the channel region and has a deeper main diffused layer than the channel region, then the high withstand voltage can be maintained even though the depth of the highly conductive region is greater than the depth of the main diffused layer to reduce the effect of a JFET formed between diffused layers of the second conductivity type.
An example of an impurity concentration distribution in the direction of the depth of the main diffused layer is shown in FIG. 30 of the accompanying drawings. The horizontal axis of FIG. 30 represents the diffused depth and the vertical axis thereof represents the impurity concentration. Since the highly conductive region is diffused into the drain layer of the same conductivity type, the diffused depth thereof should be defined. According to the present invention, the diffused depth of the highly conductive region is where the impurity concentration of the drain layer is twice the impurity concentration before the highly conductive region is formed. In FIG. 30, the depth of the main diffused layer is about 3.8 xcexcm, whereas the depth of the highly conductive region exceeds 3.8 xcexcm.
The relationship between the diffused depth, the on resistance Ron per unit area, and the breakdown voltage VDSS of the highly conductive region is shown in the graph of FIG. 31 of the accompanying drawings. In the graph, a straight line l1 represents the relationship between the on resistance Ron and the breakdown voltage VDSS in the case where the highly conductive region is formed only in the vicinity of the surface, as shown in FIG. 32a of the accompanying drawings. A straight line l2 represents the relationship between the on resistance Ron and the breakdown voltage VDSS in the case where the diffused depth of the highly conductive region is greater than the diffused depth shown in FIG. 32a, but smaller than the diffused depth of the main diffused layer, as shown in FIG. 32b of the accompanying drawings. A straight line l3 represents the relationship between the on resistance Ron and the breakdown voltage VDSS in the case where the diffused depth of the highly conductive region is smaller than the depth of a main junction, as shown in FIG. 32c of the accompanying drawings.
The graph shown in FIG. 31 indicates that as the breakdown voltage VDSS increases, the on resistance Ron increases, and the on resistance Ron is smaller as the depth of the highly conductive region is greater for the same breakdown voltage VDSS.
In the case where the highly conductive region of the first conductivity type is formed within the diffused layer of the second conductivity type including the diffused base layer, then a depletion layer in a high-resistance portion of the drain layer tends to spread easily thereby to increase the withstand voltage if the outer side of the diffused layer of the second conductivity type forms a pn junction with the high-resistance portion of the drain layer. The withstand voltage is made higher if the four corners of the diffused base layer of the second conductivity type are rounded so as not to produce spherical junctions, and also if a diffused guard ring of the second conductivity type having a diffused depth greater than the main diffused layer is disposed around the diffused base layer.
The diffused guard ring layer may be held in or out of contact with the diffused base layer of the second conductivity type. The first diffused guard ring layer may be held in contact with the diffused base layer of the second conductivity type, and the second diffused guard ring layer may be disposed around the first diffused guard ring layer out of contact therewith.
These and other features of the invention wil be understood upon reading of the following description along with the drawings.